module gen_pulse(clk,pulse44,pulse88);
input clk;
output pulse44;
output pulse88;

reg pulse44;
reg pulse88;

reg [11:0] cnt;

always@(posedge clk)begin
	if(cnt==1535)
		cnt <= 0;
	else
		cnt <= cnt +1'b1;
end

always@(posedge clk)begin
	if(cnt==0)
		pulse44 <= 1;
	else
		pulse44 <= 0;
end

always@(posedge clk)begin
	if(cnt==0 || cnt==768)
		pulse88 <= 1;
	else
		pulse88 <= 0;
end

endmodule