/* Fs=48kHz clk=6*12.288MHz=6*256*Fs SCK=12.288MHz=256*Fs BCK=64*Fs PCM4201 2's compliment */ module pcm4201(clk,bck,lrck,data,outdata); input clk; output bck; output lrck; input data; output [23:0] outdata; reg bck; reg lrck; reg [9:0] div3; reg [9:0] cnt; reg [23:0] shift_reg; reg [15:0] outdata; reg lat_data; always@(posedge clk)begin lat_data <= data; end always@(posedge clk)begin if(div3==5) div3 <=0; else div3 <= div3 + 1'b1; end always@(posedge clk)begin if(cnt==255 && div3==0) cnt <=0; else if(div3==0) cnt <= cnt + 1'b1; else cnt <= cnt; end always@(posedge clk)begin if(div3==0) bck <= cnt[1]; else bck <= bck; end always@(posedge clk)begin if(div3==0) lrck <= cnt[7]; else lrck <= lrck; end always@(posedge clk)begin if(cnt[1:0]==0 && div3==0)begin // timming+1 due to data's latch shift_reg[23:1] <= shift_reg[22:0]; shift_reg[0] <= lat_data; end else shift_reg <= shift_reg; end always@(posedge clk)begin if(cnt==226 && div3==0) // timming+1 due to data's latch outdata <= shift_reg[23:8]; else outdata <= outdata; end endmodule