Fs=48kHz
m_clk=324.576MHz=3512Fs
SCK=12.288MHz =256Fs
BCK=64Fs 

PCM1754  2's compliment

module pcm1754(m_clk,indata,sck,bck,data,lrck);
input m_clk;
input [150] indata;
output sck;
output bck;
output data;
output lrck;

reg sck;
reg bck;
reg data;
reg lrck;

reg [90] sub_cnt;

reg [90] cnt;
reg [230] shift_reg;

always@(posedge m_clk)begin
	if(sub_cnt==2)
		sub_cnt =0;
	else
		sub_cnt = sub_cnt + 1'b1;
end

always@(posedge m_clk)begin
	sck = cnt[0];
end

always@(posedge m_clk)begin
	if(cnt==511 && sub_cnt==0)
		cnt =0;
	else if(sub_cnt==0)
		cnt = cnt + 1'b1;
	else
		cnt = cnt;	
end

always@(posedge m_clk)begin
	if(sub_cnt==0)
		bck = cnt[2];
	else
		bck = bck;
end

always@(posedge m_clk)begin
	if(sub_cnt==0)
		lrck = cnt[8];
	else
		lrck = lrck;
end

always@(posedge m_clk)begin
	if(cnt==6 && sub_cnt==0 )
		shift_reg = {indata[150],8'd0};
	else if(cnt==6+256 && sub_cnt==0)
		shift_reg = {indata[150],8'd0};
	else if(cnt[20]==6 && sub_cnt==0)begin
		shift_reg[231] = shift_reg[220];
		shift_reg[0] = 0;		
	end
	else
		shift_reg = shift_reg;		
end



always@(posedge m_clk)begin
	if(sub_cnt==0)
		data = shift_reg[23] ;
	else
		data = data ;
end




endmodule