module iq_2_code(clk,I,Q,douki,outdata);
input clk;
input signed [15:0] I;
input signed [15:0] Q;
input douki;
output [7:0] outdata;

reg signed [28:0] tokushu_I; 
reg signed [28:0] tuujou_I;
reg signed [28:0] tuujou_Q;
reg signed [28:0] saved_tuujou_I;
reg signed [28:0] saved_tuujou_Q;

reg shift_douki;

reg [9:0] sub_index;
reg [9:0] index;

reg [9:0] base_const;

reg error_flg;

wire signed [31:0] temp_I;
wire signed [31:0] temp_Q;
reg signed [31:0] judge_I;
reg signed [31:0] judge_Q;
reg signed [31:0] haba;

reg [7:0] pre_out;
reg [7:0] outdata;

always@(posedge clk)begin
	shift_douki <= douki;
end

always@(posedge clk)begin
	if(shift_douki==0 && douki==1)
		sub_index <= 0;
	else if(sub_index == 767) //256*2-1
		sub_index <= 0;
	else
		sub_index <= sub_index + 1'b1;
end


always@(posedge clk)begin
	if(shift_douki==0 && douki==1)
		index <= 0;
	else if(sub_index == 767 && index!=200)
		index <= index + 1'b1;	
	else
		index <= index;	
end

always@(posedge clk)begin
	if(index==0 && sub_index==0)
		tokushu_I <= 0;
	else if(index==0 && sub_index<600)
		tokushu_I <= tokushu_I + I;
	else
		tokushu_I <= tokushu_I;		
end

always@(posedge clk)begin
	if(sub_index==0)
		tuujou_I <= 0;
	else if(sub_index<600)
		tuujou_I <= tuujou_I + I;
	else
		tuujou_I <= tuujou_I;		
end

always@(posedge clk)begin
	if(sub_index==0)
		tuujou_Q <= 0;
	else if(sub_index<600)
		tuujou_Q <= tuujou_Q + Q;
	else
		tuujou_Q <= tuujou_Q;		
end

always@(posedge clk)begin
	if(sub_index==602)
		saved_tuujou_I <= tuujou_I;
	else
		saved_tuujou_I <= saved_tuujou_I;		
end

always@(posedge clk)begin
	if(sub_index==602)
		saved_tuujou_Q <= tuujou_Q;
	else
		saved_tuujou_Q <= saved_tuujou_Q;		
end

always@(posedge clk)begin
	if(sub_index==602)
		base_const <= 0;
	else if(base_const!=259)
		base_const <= base_const + 1'b1;
	else
		base_const <= base_const;		
end



assign temp_I=base_const[3:0];
assign temp_Q=base_const[7:4];


always@(posedge clk)begin
	judge_I <= ((temp_I*2-7)*tokushu_I)/16;	
	judge_Q <= ((temp_Q*2-7)*tokushu_I)/16;	
end

always@(posedge clk)begin
	haba <= tokushu_I/64;	
end

always@(posedge clk)begin
	if(sub_index==602)
		error_flg <= 1;
	else if(judge_I-haba <= saved_tuujou_I  && judge_I+haba >= saved_tuujou_I  && judge_Q-haba <= saved_tuujou_Q  && judge_Q+haba >= saved_tuujou_Q && base_const<=256)
		error_flg <= 0;
	else
		error_flg <= error_flg;		
end

always@(posedge clk)begin
	if(judge_I-haba <= saved_tuujou_I  && judge_I+haba >= saved_tuujou_I  && judge_Q-haba <= saved_tuujou_Q  && judge_Q+haba >= saved_tuujou_Q  && base_const<=256)
		pre_out <= base_const-1;
	else
		pre_out <= pre_out;		
end

always@(posedge clk)begin
	if(base_const==258 && error_flg==0)
		outdata <= pre_out;
	else if(base_const==258 && error_flg==1)
		outdata <= 0;
	else
		outdata <= outdata;		
end

endmodule