module det_tokushu_code(clk,indata,douki,det_pulse);
input clk;
input signed [15:0] indata;
output douki;
output det_pulse;

reg douki;
reg det_pulse;

reg signed [16:0] abs_indata;
reg [15:0] shift_abs0;
reg [15:0] shift_abs1;
reg [15:0] shift_abs2;
reg [15:0] shift_abs3;
reg [15:0] shift_abs4;
reg [15:0] shift_abs5;
reg [15:0] shift_abs6;
reg [15:0] shift_abs7;
reg [15:0] shift_abs8;
reg [15:0] shift_abs9;
reg [15:0] shift_abs10;
reg [15:0] shift_abs11;
reg [15:0] shift_abs12;
reg [15:0] shift_abs13;
reg [15:0] shift_abs14;
reg [15:0] shift_abs15;

reg [19:0] sum0_0;
reg [19:0] sum0_1;
reg [19:0] sum0_2;
reg [19:0] sum0_3; 
reg [19:0] sum; 

reg [19:0] det_mask;


always@(posedge clk)begin
	if(indata<0)
		abs_indata <= (-1)*indata;
	else
		abs_indata <= indata;		
end

always@(posedge clk)begin
	shift_abs0 <= 	abs_indata;
	shift_abs1 <= 	shift_abs0;
	shift_abs2 <= 	shift_abs1;	
	shift_abs3 <= 	shift_abs2;
	shift_abs4 <= 	shift_abs3;	
	shift_abs5 <= 	shift_abs4;
	shift_abs6 <= 	shift_abs5;	
	shift_abs7 <= 	shift_abs6;
	shift_abs8 <= 	shift_abs7;	
	shift_abs9 <= 	shift_abs8;
	shift_abs10 <= 	shift_abs9;	
	shift_abs11 <= 	shift_abs10;
	shift_abs12 <= 	shift_abs11;	
	shift_abs13 <= 	shift_abs12;
	shift_abs14 <= 	shift_abs13;	
	shift_abs15 <= 	shift_abs14;
end


always@(posedge clk)begin
	sum0_0 <= 	shift_abs0 + shift_abs1 + shift_abs2 + shift_abs3;
	sum0_1 <= 	shift_abs4 + shift_abs5 + shift_abs6 + shift_abs7;
	sum0_2 <= 	shift_abs8 + shift_abs9 + shift_abs10 + shift_abs11;
	sum0_3 <= 	shift_abs12 + shift_abs13 + shift_abs11 + shift_abs15;
	sum <= 	sum0_0 + sum0_1 + sum0_2 + sum0_3;
end


always@(posedge clk)begin
	if(det_mask==100000 && sum<320)
		det_mask <= 0;
	else if(det_mask!=100000)
		det_mask <= det_mask + 1'b1;	
	else
		det_mask <= det_mask;			
end


always@(posedge clk)begin
	if(det_mask==100000 && sum<320)
		det_pulse <= 1;
	else
		det_pulse <= 0;			
end


always@(posedge clk)begin
	if(det_mask>800  && det_mask<1400 )
		douki <= 1;
	else
		douki <= 0;			
end

endmodule